A COMMON APPROACH TO TEST GENERATION AND HARDWARE VERIFICATION BASED ON TEMPORAL LOGIC - Test Conference, 1991, Proceedings., International
نویسندگان
چکیده
Hardware verification and sequemio/ leSI genera/ion are aspects of the same problem. namely /0 prove the equal behavior determined by two circuit descriptions. During test generatjon, this altempi succeeds for the faulty and fault free circuil if redundancy exisis, and during verification it succeeds. if the implemenlofion is correct with regard to ils specification. This observation can be used 10 cross{erli/ize both areas, which hnvc been treated separately up 10 now. In this paper, a common jorl1UJl framework/or hardware verification and sequential/est pattern generalion is presented. which is based on modeling Ihe circuil behavior wilh temporal/ogic. In addition, a new approach 10 cope wilh non reselable flip flops in sequential lest generation is proposed, which is nol reslricled to sluck·at faults. Based on this verification view, it is pass;· ble to provide the designer with one tool for checking cir· cuit correctness and generating test patterns. Its first implementation WId application is olso described.
منابع مشابه
A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic
Hardware verification and sequential test generation are aspects of the same problem, namely to prove the equal behavior determined by two circuit descriptions. During test generation, this attempt succeeds for the faulty and fault free circuit if redundancy exists, and during verification it succeeds, if the implementation is correct with regard to its specification. This observation can be us...
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